1. Field of the Invention
This invention relates to digital integrated circuits, and more particularly to input/output (I/O) buffer circuits connected to I/O pads of integrated circuits and to terminals of semiconductor device packages.
2. Description of the Relevant Art
Digital electronic devices typically communicate via electrical signals (e.g., voltage and/or current) driven upon electrical conductors (e.g., metal wires). Simultaneous transmission of multiple signals is accommodated by several signal lines routed in parallel (i.e., buses). Most computer systems have a modular architecture centered around a bus which serves as a shared communication link between system components. The two major advantages of shared buses over direct communication links between system components are versatility and low cost. By defining a standard interconnection scheme for a given bus, new devices may be easily connected to the bus. The cost of the bus is low because it is shared among the number of components connected to the bus.
As the operating frequencies (i.e., "speeds") of digital electronic devices increase, the signal lines used to route signals between components begin to behave like transmission lines. Transmission lines have characteristic impedances. If the input impedance of a receiving component connected to a transmission line does not match the characteristic impedance of the transmission line, a portion of an incoming signal is reflected back toward a sending component. Such reflections cause the received signal to be distorted. If the distortion is great enough, the receiving component may erroneously interpret the logical value of the incoming signal.
Digital signals have logic low (i.e., "0") levels, logic high (i.e., "1") levels, "rise times" associated with transitions from the logic low level to the logic high level, and "fall times" associated with transitions from the logic high level to the logic low level. A signal line behaves like a transmission line when the signal rise time (or signal fall time) is short with respect to time required for the signal tore the length of the signal line (i.e., the propagation delay time of the signal line). As a general rule, a signal line behaves like a transmission line when the propagation delay time of the signal line is greater than about one-quarter of the signal rise time (or signal fall time).
Resistive "termination" techniques are often applied to signal lines long enough to behave like transmission lines in order to reduce reflections and the resultant signal distortion. One or more electrically resistive elements are added between each sending component and the signal line (i.e., transmission line) in order to cause the effective output impedances of the sending components to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements are added between each receiving component and the transmission line in order to cause the effective input impedances of the receiving components to more closely match the characteristic impedance of the transmission line.
Several new buses have been developed to meet the needs of high-frequency (i.e., "fast") digital electronic devices, one of which is based upon Gunning Transceiver Logic (GTL). GTL bus technology employs resistive termination of signal lines, and reduces current flowing through pull-up resistors (typically 50 ohms) placed at opposite ends of each signal line by using a relatively small termination voltage (typically 1.2 volts). A GTL driver is typically an open drain n-channel metal oxide semiconductor (MOS) transistor. An external pull-up resistor (typically 50 ohms) connects the drain of the n-channel transistor to the termination voltage. A GTL receiver is typically a differential amplifier with one terminal connected to a reference voltage (typically 0.8 volts).
Employing a high performance bus technology such as GTL within an existing system requires that all the input/output (I/O) buffers within each component connected to the GTL bus be redesigned. With modern packaged integrated circuits having hundreds of terminals, this alone is a substantial undertaking. In addition, the new components containing the redesigned I/O buffers may not support older bus standards.
It would be beneficial to have an I/O buffer which selectively provides resistive termination required to support higher performance buses (i.e., increased data transfer rates). Such an I/O buffer would be able to provide the impedance matching required by higher performance bus technologies while maintaining the ability to support older bus standards not requiring resistive termination.